powerpc updates for 6.14

- Add preempt lazy support
 
  - Deprecate cxl and cxl flash driver
 
  - Fix a possible IOMMU related OOPS at boot on pSeries
 
  - Optimize sched_clock() in ppc32 by replacing mulhdu() by mul_u64_u64_shr()
 
 Thanks to: Andrew Donnellan, Andy Shevchenko, Ankur Arora, Christophe Leroy,
 Frederic Barrat, Gaurav Batra, Luis Felipe Hernandez, Michael Ellerman, Nilay
 Shroff, Ricardo B. Marliere, Ritesh Harjani (IBM), Sebastian Andrzej Siewior,
 Shrikanth Hegde, Sourabh Jain, Thorsten Blum, Zhu Jun.
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Merge tag 'powerpc-6.14-1' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux

Pull powerpc updates from Madhavan Srinivasan:

 - Add preempt lazy support

 - Deprecate cxl and cxl flash driver

 - Fix a possible IOMMU related OOPS at boot on pSeries

 - Optimize sched_clock() in ppc32 by replacing mulhdu() by
   mul_u64_u64_shr()

Thanks to Andrew Donnellan, Andy Shevchenko, Ankur Arora, Christophe
Leroy, Frederic Barrat, Gaurav Batra, Luis Felipe Hernandez, Michael
Ellerman, Nilay Shroff, Ricardo B.  Marliere, Ritesh Harjani (IBM),
Sebastian Andrzej Siewior, Shrikanth Hegde, Sourabh Jain, Thorsten Blum,
and Zhu Jun.

* tag 'powerpc-6.14-1' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux:
  selftests/powerpc: Fix argument order to timer_sub()
  powerpc/prom_init: Use IS_ENABLED()
  powerpc/pseries/iommu: IOMMU incorrectly marks MMIO range in DDW
  powerpc: Use str_on_off() helper in check_cache_coherency()
  powerpc: Large user copy aware of full:rt:lazy preemption
  powerpc: Add preempt lazy support
  powerpc/book3s64/hugetlb: Fix disabling hugetlb when fadump is active
  powerpc/vdso: Mark the vDSO code read-only after init
  powerpc/64: Use get_user() in start_thread()
  macintosh: declare ctl_table as const
  selftest/powerpc/ptrace: Cleanup duplicate macro definitions
  selftest/powerpc/ptrace/ptrace-pkey: Remove duplicate macros
  selftest/powerpc/ptrace/core-pkey: Remove duplicate macros
  powerpc/8xx: Drop legacy-of-mm-gpiochip.h header
  scsi/cxlflash: Deprecate driver
  cxl: Deprecate driver
  selftests/powerpc: Fix typo in test-vphn.c
  powerpc/xmon: Use str_yes_no() helper in dump_one_paca()
  powerpc/32: Replace mulhdu() by mul_u64_u64_shr()
This commit is contained in:
Linus Torvalds 2025-01-20 21:40:19 -08:00
commit 95ec54a420
29 changed files with 142 additions and 194 deletions

View File

@ -1,3 +1,6 @@
The cxl driver is no longer maintained, and will be removed from the kernel in
the near future.
Please note that attributes that are shared between devices are stored in
the directory pointed to by the symlink device/.
For example, the real path of the attribute /sys/class/cxl/afu0.0s/irqs_max is

View File

@ -6226,8 +6226,8 @@ CXL (IBM Coherent Accelerator Processor Interface CAPI) DRIVER
M: Frederic Barrat <fbarrat@linux.ibm.com>
M: Andrew Donnellan <ajd@linux.ibm.com>
L: linuxppc-dev@lists.ozlabs.org
S: Supported
F: Documentation/ABI/testing/sysfs-class-cxl
S: Obsolete
F: Documentation/ABI/obsolete/sysfs-class-cxl
F: Documentation/arch/powerpc/cxl.rst
F: arch/powerpc/platforms/powernv/pci-cxl.c
F: drivers/misc/cxl/

View File

@ -145,6 +145,7 @@ config PPC
select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
select ARCH_HAS_PHYS_TO_DMA
select ARCH_HAS_PMEM_API
select ARCH_HAS_PREEMPT_LAZY
select ARCH_HAS_PTE_DEVMAP if PPC_BOOK3S_64
select ARCH_HAS_PTE_SPECIAL
select ARCH_HAS_SCALED_CPUTIME if VIRT_CPU_ACCOUNTING_NATIVE && PPC_BOOK3S_64

View File

@ -15,6 +15,15 @@
extern bool hugetlb_disabled;
static inline bool hugepages_supported(void)
{
if (hugetlb_disabled)
return false;
return HPAGE_SHIFT != 0;
}
#define hugepages_supported hugepages_supported
void __init hugetlbpage_init_defaultsize(void);
int slice_is_hugepage_only_range(struct mm_struct *mm, unsigned long addr,

View File

@ -103,6 +103,7 @@ void arch_setup_new_exec(void);
#define TIF_PATCH_PENDING 6 /* pending live patching update */
#define TIF_SYSCALL_AUDIT 7 /* syscall auditing active */
#define TIF_SINGLESTEP 8 /* singlestepping active */
#define TIF_NEED_RESCHED_LAZY 9 /* Scheduler driven lazy preemption */
#define TIF_SECCOMP 10 /* secure computing */
#define TIF_RESTOREALL 11 /* Restore all regs (implies NOERROR) */
#define TIF_NOERROR 12 /* Force successful syscall return */
@ -122,6 +123,7 @@ void arch_setup_new_exec(void);
#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE)
#define _TIF_SIGPENDING (1<<TIF_SIGPENDING)
#define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED)
#define _TIF_NEED_RESCHED_LAZY (1<<TIF_NEED_RESCHED_LAZY)
#define _TIF_NOTIFY_SIGNAL (1<<TIF_NOTIFY_SIGNAL)
#define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG)
#define _TIF_32BIT (1<<TIF_32BIT)
@ -142,9 +144,10 @@ void arch_setup_new_exec(void);
_TIF_SYSCALL_EMU)
#define _TIF_USER_WORK_MASK (_TIF_SIGPENDING | _TIF_NEED_RESCHED | \
_TIF_NOTIFY_RESUME | _TIF_UPROBE | \
_TIF_RESTORE_TM | _TIF_PATCH_PENDING | \
_TIF_NOTIFY_SIGNAL)
_TIF_NEED_RESCHED_LAZY | _TIF_NOTIFY_RESUME | \
_TIF_UPROBE | _TIF_RESTORE_TM | \
_TIF_PATCH_PENDING | _TIF_NOTIFY_SIGNAL)
#define _TIF_PERSYSCALL_MASK (_TIF_RESTOREALL|_TIF_NOERROR)
/* Bits in local_flags */

View File

@ -86,7 +86,7 @@ static inline unsigned long tb_ticks_since(unsigned long tstamp)
#define mulhdu(x,y) \
({unsigned long z; asm ("mulhdu %0,%1,%2" : "=r" (z) : "r" (x), "r" (y)); z;})
#else
extern u64 mulhdu(u64, u64);
#define mulhdu(x, y) mul_u64_u64_shr(x, y, 64)
#endif
extern void div128_by_32(u64 dividend_high, u64 dividend_low,

View File

@ -185,7 +185,7 @@ interrupt_exit_user_prepare_main(unsigned long ret, struct pt_regs *regs)
ti_flags = read_thread_flags();
while (unlikely(ti_flags & (_TIF_USER_WORK_MASK & ~_TIF_RESTORE_TM))) {
local_irq_enable();
if (ti_flags & _TIF_NEED_RESCHED) {
if (ti_flags & (_TIF_NEED_RESCHED | _TIF_NEED_RESCHED_LAZY)) {
schedule();
} else {
/*
@ -396,7 +396,7 @@ notrace unsigned long interrupt_exit_kernel_prepare(struct pt_regs *regs)
/* Returning to a kernel context with local irqs enabled. */
WARN_ON_ONCE(!(regs->msr & MSR_EE));
again:
if (IS_ENABLED(CONFIG_PREEMPT)) {
if (IS_ENABLED(CONFIG_PREEMPTION)) {
/* Return to preemptible kernel context */
if (unlikely(read_thread_flags() & _TIF_NEED_RESCHED)) {
if (preempt_count() == 0)

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@ -687,7 +687,7 @@ void iommu_table_clear(struct iommu_table *tbl)
void iommu_table_reserve_pages(struct iommu_table *tbl,
unsigned long res_start, unsigned long res_end)
{
int i;
unsigned long i;
WARN_ON_ONCE(res_end < res_start);
/*

View File

@ -27,32 +27,6 @@
.text
/*
* This returns the high 64 bits of the product of two 64-bit numbers.
*/
_GLOBAL(mulhdu)
cmpwi r6,0
cmpwi cr1,r3,0
mr r10,r4
mulhwu r4,r4,r5
beq 1f
mulhwu r0,r10,r6
mullw r7,r10,r5
addc r7,r0,r7
addze r4,r4
1: beqlr cr1 /* all done if high part of A is 0 */
mullw r9,r3,r5
mulhwu r10,r3,r5
beq 2f
mullw r0,r3,r6
mulhwu r8,r3,r6
addc r7,r0,r7
adde r4,r4,r8
addze r10,r10
2: addc r4,r4,r9
addze r3,r10
blr
/*
* reloc_got2 runs through the .got2 section adding an offset
* to each entry.

View File

@ -1960,8 +1960,8 @@ void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp)
* address of _start and the second entry is the TOC
* value we need to use.
*/
__get_user(entry, (unsigned long __user *)start);
__get_user(toc, (unsigned long __user *)start+1);
get_user(entry, (unsigned long __user *)start);
get_user(toc, (unsigned long __user *)start+1);
/* Check whether the e_entry function descriptor entries
* need to be relocated before we can use them.

View File

@ -2792,7 +2792,6 @@ static void __init flatten_device_tree(void)
dt_struct_start, dt_struct_end);
}
#ifdef CONFIG_PPC_CHRP
/*
* Pegasos and BriQ lacks the "ranges" property in the isa node
* Pegasos needs decimal IRQ 14/15, not hexadecimal
@ -2843,11 +2842,7 @@ static void __init fixup_device_tree_chrp(void)
}
}
}
#else
#define fixup_device_tree_chrp()
#endif
#if defined(CONFIG_PPC64) && defined(CONFIG_PPC_PMAC)
static void __init fixup_device_tree_pmac64(void)
{
phandle u3, i2c, mpic;
@ -2887,11 +2882,7 @@ static void __init fixup_device_tree_pmac64(void)
prom_setprop(i2c, "/u3@0,f8000000/i2c@f8001000", "interrupt-parent",
&parent, sizeof(parent));
}
#else
#define fixup_device_tree_pmac64()
#endif
#ifdef CONFIG_PPC_PMAC
static void __init fixup_device_tree_pmac(void)
{
__be32 val = 1;
@ -2911,11 +2902,7 @@ static void __init fixup_device_tree_pmac(void)
prom_setprop(node, NULL, "#size-cells", &val, sizeof(val));
}
}
#else
static inline void fixup_device_tree_pmac(void) { }
#endif
#ifdef CONFIG_PPC_EFIKA
/*
* The MPC5200 FEC driver requires an phy-handle property to tell it how
* to talk to the phy. If the phy-handle property is missing, then this
@ -3047,11 +3034,7 @@ static void __init fixup_device_tree_efika(void)
/* Make sure ethernet phy-handle property exists */
fixup_device_tree_efika_add_phy();
}
#else
#define fixup_device_tree_efika()
#endif
#ifdef CONFIG_PPC_PASEMI_NEMO
/*
* CFE supplied on Nemo is broken in several ways, biggest
* problem is that it reassigns ISA interrupts to unused mpic ints.
@ -3127,17 +3110,23 @@ static void __init fixup_device_tree_pasemi(void)
prom_setprop(iob, name, "device_type", "isa", sizeof("isa"));
}
#else /* !CONFIG_PPC_PASEMI_NEMO */
static inline void fixup_device_tree_pasemi(void) { }
#endif
static void __init fixup_device_tree(void)
{
fixup_device_tree_chrp();
fixup_device_tree_pmac();
fixup_device_tree_pmac64();
fixup_device_tree_efika();
fixup_device_tree_pasemi();
if (IS_ENABLED(CONFIG_PPC_CHRP))
fixup_device_tree_chrp();
if (IS_ENABLED(CONFIG_PPC_PMAC))
fixup_device_tree_pmac();
if (IS_ENABLED(CONFIG_PPC_PMAC) && IS_ENABLED(CONFIG_PPC64))
fixup_device_tree_pmac64();
if (IS_ENABLED(CONFIG_PPC_EFIKA))
fixup_device_tree_efika();
if (IS_ENABLED(CONFIG_PPC_PASEMI_NEMO))
fixup_device_tree_pasemi();
}
static void __init prom_find_boot_cpu(void)

View File

@ -834,8 +834,8 @@ static int __init check_cache_coherency(void)
if (devtree_coherency != KERNEL_COHERENCY) {
printk(KERN_ERR
"kernel coherency:%s != device tree_coherency:%s\n",
KERNEL_COHERENCY ? "on" : "off",
devtree_coherency ? "on" : "off");
str_on_off(KERNEL_COHERENCY),
str_on_off(devtree_coherency));
BUG();
}

View File

@ -2,7 +2,7 @@
#include <linux/linkage.h>
#include <asm/page.h>
__PAGE_ALIGNED_DATA
.section ".data..ro_after_init", "aw"
.globl vdso32_start, vdso32_end
.balign PAGE_SIZE

View File

@ -2,7 +2,7 @@
#include <linux/linkage.h>
#include <asm/page.h>
__PAGE_ALIGNED_DATA
.section ".data..ro_after_init", "aw"
.globl vdso64_start, vdso64_end
.balign PAGE_SIZE

View File

@ -45,7 +45,7 @@ int exit_vmx_usercopy(void)
* set and we are preemptible. The hack here is to schedule a
* decrementer to fire here and reschedule for us if necessary.
*/
if (IS_ENABLED(CONFIG_PREEMPT) && need_resched())
if (IS_ENABLED(CONFIG_PREEMPTION) && need_resched())
set_dec(1);
return 0;
}

View File

@ -45,7 +45,7 @@
#include <sysdev/fsl_soc.h>
#ifdef CONFIG_8xx_GPIO
#include <linux/gpio/legacy-of-mm-gpiochip.h>
#include <linux/gpio/driver.h>
#endif
#define CPM_MAP_SIZE (0x4000)
@ -376,7 +376,8 @@ int __init cpm1_clk_setup(enum cpm_clk_target target, int clock, int mode)
#ifdef CONFIG_8xx_GPIO
struct cpm1_gpio16_chip {
struct of_mm_gpio_chip mm_gc;
struct gpio_chip gc;
void __iomem *regs;
spinlock_t lock;
/* shadowed data register to clear/set bits safely */
@ -386,19 +387,17 @@ struct cpm1_gpio16_chip {
int irq[16];
};
static void cpm1_gpio16_save_regs(struct of_mm_gpio_chip *mm_gc)
static void cpm1_gpio16_save_regs(struct cpm1_gpio16_chip *cpm1_gc)
{
struct cpm1_gpio16_chip *cpm1_gc =
container_of(mm_gc, struct cpm1_gpio16_chip, mm_gc);
struct cpm_ioport16 __iomem *iop = mm_gc->regs;
struct cpm_ioport16 __iomem *iop = cpm1_gc->regs;
cpm1_gc->cpdata = in_be16(&iop->dat);
}
static int cpm1_gpio16_get(struct gpio_chip *gc, unsigned int gpio)
{
struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
struct cpm_ioport16 __iomem *iop = mm_gc->regs;
struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(gc);
struct cpm_ioport16 __iomem *iop = cpm1_gc->regs;
u16 pin_mask;
pin_mask = 1 << (15 - gpio);
@ -406,11 +405,9 @@ static int cpm1_gpio16_get(struct gpio_chip *gc, unsigned int gpio)
return !!(in_be16(&iop->dat) & pin_mask);
}
static void __cpm1_gpio16_set(struct of_mm_gpio_chip *mm_gc, u16 pin_mask,
int value)
static void __cpm1_gpio16_set(struct cpm1_gpio16_chip *cpm1_gc, u16 pin_mask, int value)
{
struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
struct cpm_ioport16 __iomem *iop = mm_gc->regs;
struct cpm_ioport16 __iomem *iop = cpm1_gc->regs;
if (value)
cpm1_gc->cpdata |= pin_mask;
@ -422,38 +419,35 @@ static void __cpm1_gpio16_set(struct of_mm_gpio_chip *mm_gc, u16 pin_mask,
static void cpm1_gpio16_set(struct gpio_chip *gc, unsigned int gpio, int value)
{
struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(gc);
unsigned long flags;
u16 pin_mask = 1 << (15 - gpio);
spin_lock_irqsave(&cpm1_gc->lock, flags);
__cpm1_gpio16_set(mm_gc, pin_mask, value);
__cpm1_gpio16_set(cpm1_gc, pin_mask, value);
spin_unlock_irqrestore(&cpm1_gc->lock, flags);
}
static int cpm1_gpio16_to_irq(struct gpio_chip *gc, unsigned int gpio)
{
struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(gc);
return cpm1_gc->irq[gpio] ? : -ENXIO;
}
static int cpm1_gpio16_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
{
struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
struct cpm_ioport16 __iomem *iop = mm_gc->regs;
struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(gc);
struct cpm_ioport16 __iomem *iop = cpm1_gc->regs;
unsigned long flags;
u16 pin_mask = 1 << (15 - gpio);
spin_lock_irqsave(&cpm1_gc->lock, flags);
setbits16(&iop->dir, pin_mask);
__cpm1_gpio16_set(mm_gc, pin_mask, val);
__cpm1_gpio16_set(cpm1_gc, pin_mask, val);
spin_unlock_irqrestore(&cpm1_gc->lock, flags);
@ -462,9 +456,8 @@ static int cpm1_gpio16_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
static int cpm1_gpio16_dir_in(struct gpio_chip *gc, unsigned int gpio)
{
struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
struct cpm_ioport16 __iomem *iop = mm_gc->regs;
struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(gc);
struct cpm_ioport16 __iomem *iop = cpm1_gc->regs;
unsigned long flags;
u16 pin_mask = 1 << (15 - gpio);
@ -481,11 +474,10 @@ int cpm1_gpiochip_add16(struct device *dev)
{
struct device_node *np = dev->of_node;
struct cpm1_gpio16_chip *cpm1_gc;
struct of_mm_gpio_chip *mm_gc;
struct gpio_chip *gc;
u16 mask;
cpm1_gc = kzalloc(sizeof(*cpm1_gc), GFP_KERNEL);
cpm1_gc = devm_kzalloc(dev, sizeof(*cpm1_gc), GFP_KERNEL);
if (!cpm1_gc)
return -ENOMEM;
@ -499,10 +491,8 @@ int cpm1_gpiochip_add16(struct device *dev)
cpm1_gc->irq[i] = irq_of_parse_and_map(np, j++);
}
mm_gc = &cpm1_gc->mm_gc;
gc = &mm_gc->gc;
mm_gc->save_regs = cpm1_gpio16_save_regs;
gc = &cpm1_gc->gc;
gc->base = -1;
gc->ngpio = 16;
gc->direction_input = cpm1_gpio16_dir_in;
gc->direction_output = cpm1_gpio16_dir_out;
@ -512,30 +502,39 @@ int cpm1_gpiochip_add16(struct device *dev)
gc->parent = dev;
gc->owner = THIS_MODULE;
return of_mm_gpiochip_add_data(np, mm_gc, cpm1_gc);
gc->label = devm_kasprintf(dev, GFP_KERNEL, "%pOF", np);
if (!gc->label)
return -ENOMEM;
cpm1_gc->regs = devm_of_iomap(dev, np, 0, NULL);
if (IS_ERR(cpm1_gc->regs))
return PTR_ERR(cpm1_gc->regs);
cpm1_gpio16_save_regs(cpm1_gc);
return devm_gpiochip_add_data(dev, gc, cpm1_gc);
}
struct cpm1_gpio32_chip {
struct of_mm_gpio_chip mm_gc;
struct gpio_chip gc;
void __iomem *regs;
spinlock_t lock;
/* shadowed data register to clear/set bits safely */
u32 cpdata;
};
static void cpm1_gpio32_save_regs(struct of_mm_gpio_chip *mm_gc)
static void cpm1_gpio32_save_regs(struct cpm1_gpio32_chip *cpm1_gc)
{
struct cpm1_gpio32_chip *cpm1_gc =
container_of(mm_gc, struct cpm1_gpio32_chip, mm_gc);
struct cpm_ioport32b __iomem *iop = mm_gc->regs;
struct cpm_ioport32b __iomem *iop = cpm1_gc->regs;
cpm1_gc->cpdata = in_be32(&iop->dat);
}
static int cpm1_gpio32_get(struct gpio_chip *gc, unsigned int gpio)
{
struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
struct cpm_ioport32b __iomem *iop = mm_gc->regs;
struct cpm1_gpio32_chip *cpm1_gc = gpiochip_get_data(gc);
struct cpm_ioport32b __iomem *iop = cpm1_gc->regs;
u32 pin_mask;
pin_mask = 1 << (31 - gpio);
@ -543,11 +542,9 @@ static int cpm1_gpio32_get(struct gpio_chip *gc, unsigned int gpio)
return !!(in_be32(&iop->dat) & pin_mask);
}
static void __cpm1_gpio32_set(struct of_mm_gpio_chip *mm_gc, u32 pin_mask,
int value)
static void __cpm1_gpio32_set(struct cpm1_gpio32_chip *cpm1_gc, u32 pin_mask, int value)
{
struct cpm1_gpio32_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
struct cpm_ioport32b __iomem *iop = mm_gc->regs;
struct cpm_ioport32b __iomem *iop = cpm1_gc->regs;
if (value)
cpm1_gc->cpdata |= pin_mask;
@ -559,30 +556,28 @@ static void __cpm1_gpio32_set(struct of_mm_gpio_chip *mm_gc, u32 pin_mask,
static void cpm1_gpio32_set(struct gpio_chip *gc, unsigned int gpio, int value)
{
struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
struct cpm1_gpio32_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
struct cpm1_gpio32_chip *cpm1_gc = gpiochip_get_data(gc);
unsigned long flags;
u32 pin_mask = 1 << (31 - gpio);
spin_lock_irqsave(&cpm1_gc->lock, flags);
__cpm1_gpio32_set(mm_gc, pin_mask, value);
__cpm1_gpio32_set(cpm1_gc, pin_mask, value);
spin_unlock_irqrestore(&cpm1_gc->lock, flags);
}
static int cpm1_gpio32_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
{
struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
struct cpm1_gpio32_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
struct cpm_ioport32b __iomem *iop = mm_gc->regs;
struct cpm1_gpio32_chip *cpm1_gc = gpiochip_get_data(gc);
struct cpm_ioport32b __iomem *iop = cpm1_gc->regs;
unsigned long flags;
u32 pin_mask = 1 << (31 - gpio);
spin_lock_irqsave(&cpm1_gc->lock, flags);
setbits32(&iop->dir, pin_mask);
__cpm1_gpio32_set(mm_gc, pin_mask, val);
__cpm1_gpio32_set(cpm1_gc, pin_mask, val);
spin_unlock_irqrestore(&cpm1_gc->lock, flags);
@ -591,9 +586,8 @@ static int cpm1_gpio32_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
static int cpm1_gpio32_dir_in(struct gpio_chip *gc, unsigned int gpio)
{
struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
struct cpm1_gpio32_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
struct cpm_ioport32b __iomem *iop = mm_gc->regs;
struct cpm1_gpio32_chip *cpm1_gc = gpiochip_get_data(gc);
struct cpm_ioport32b __iomem *iop = cpm1_gc->regs;
unsigned long flags;
u32 pin_mask = 1 << (31 - gpio);
@ -610,19 +604,16 @@ int cpm1_gpiochip_add32(struct device *dev)
{
struct device_node *np = dev->of_node;
struct cpm1_gpio32_chip *cpm1_gc;
struct of_mm_gpio_chip *mm_gc;
struct gpio_chip *gc;
cpm1_gc = kzalloc(sizeof(*cpm1_gc), GFP_KERNEL);
cpm1_gc = devm_kzalloc(dev, sizeof(*cpm1_gc), GFP_KERNEL);
if (!cpm1_gc)
return -ENOMEM;
spin_lock_init(&cpm1_gc->lock);
mm_gc = &cpm1_gc->mm_gc;
gc = &mm_gc->gc;
mm_gc->save_regs = cpm1_gpio32_save_regs;
gc = &cpm1_gc->gc;
gc->base = -1;
gc->ngpio = 32;
gc->direction_input = cpm1_gpio32_dir_in;
gc->direction_output = cpm1_gpio32_dir_out;
@ -631,7 +622,17 @@ int cpm1_gpiochip_add32(struct device *dev)
gc->parent = dev;
gc->owner = THIS_MODULE;
return of_mm_gpiochip_add_data(np, mm_gc, cpm1_gc);
gc->label = devm_kasprintf(dev, GFP_KERNEL, "%pOF", np);
if (!gc->label)
return -ENOMEM;
cpm1_gc->regs = devm_of_iomap(dev, np, 0, NULL);
if (IS_ERR(cpm1_gc->regs))
return PTR_ERR(cpm1_gc->regs);
cpm1_gpio32_save_regs(cpm1_gc);
return devm_gpiochip_add_data(dev, gc, cpm1_gc);
}
#endif /* CONFIG_8xx_GPIO */

View File

@ -1650,7 +1650,8 @@ static bool enable_ddw(struct pci_dev *dev, struct device_node *pdn)
iommu_table_setparms_common(newtbl, pci->phb->bus->number, create.liobn,
dynamic_addr, dynamic_len, page_shift, NULL,
&iommu_table_lpar_multi_ops);
iommu_init_table(newtbl, pci->phb->node, start, end);
iommu_init_table(newtbl, pci->phb->node,
start >> page_shift, end >> page_shift);
pci->table_group->tables[default_win_removed ? 0 : 1] = newtbl;
@ -2065,7 +2066,9 @@ static long spapr_tce_create_table(struct iommu_table_group *table_group, int nu
offset, 1UL << window_shift,
IOMMU_PAGE_SHIFT_4K, NULL,
&iommu_table_lpar_multi_ops);
iommu_init_table(tbl, pci->phb->node, start, end);
iommu_init_table(tbl, pci->phb->node,
start >> IOMMU_PAGE_SHIFT_4K,
end >> IOMMU_PAGE_SHIFT_4K);
table_group->tables[0] = tbl;
@ -2136,7 +2139,7 @@ static long spapr_tce_create_table(struct iommu_table_group *table_group, int nu
/* New table for using DDW instead of the default DMA window */
iommu_table_setparms_common(tbl, pci->phb->bus->number, create.liobn, win_addr,
1UL << len, page_shift, NULL, &iommu_table_lpar_multi_ops);
iommu_init_table(tbl, pci->phb->node, start, end);
iommu_init_table(tbl, pci->phb->node, start >> page_shift, end >> page_shift);
pci->table_group->tables[num] = tbl;
set_iommu_table_base(&pdev->dev, tbl);

View File

@ -2623,9 +2623,9 @@ static void dump_one_paca(int cpu)
printf("paca for cpu 0x%x @ %px:\n", cpu, p);
printf(" %-*s = %s\n", 25, "possible", cpu_possible(cpu) ? "yes" : "no");
printf(" %-*s = %s\n", 25, "present", cpu_present(cpu) ? "yes" : "no");
printf(" %-*s = %s\n", 25, "online", cpu_online(cpu) ? "yes" : "no");
printf(" %-*s = %s\n", 25, "possible", str_yes_no(cpu_possible(cpu)));
printf(" %-*s = %s\n", 25, "present", str_yes_no(cpu_present(cpu)));
printf(" %-*s = %s\n", 25, "online", str_yes_no(cpu_online(cpu)));
#define DUMP(paca, name, format) \
printf(" %-*s = "format"\t(0x%lx)\n", 25, #name, 18, paca->name, \

View File

@ -215,7 +215,7 @@ static int mac_hid_toggle_emumouse(const struct ctl_table *table, int write,
}
/* file(s) in /proc/sys/dev/mac_hid */
static struct ctl_table mac_hid_files[] = {
static const struct ctl_table mac_hid_files[] = {
{
.procname = "mouse_button_emulation",
.data = &mouse_emulate_buttons,

View File

@ -9,11 +9,13 @@ config CXL_BASE
select PPC_64S_HASH_MMU
config CXL
tristate "Support for IBM Coherent Accelerators (CXL)"
tristate "Support for IBM Coherent Accelerators (CXL) (DEPRECATED)"
depends on PPC_POWERNV && PCI_MSI && EEH
select CXL_BASE
default m
help
The cxl driver is deprecated and will be removed in a future
kernel release.
Select this option to enable driver support for IBM Coherent
Accelerators (CXL). CXL is otherwise known as Coherent Accelerator
Processor Interface (CAPI). CAPI allows accelerators in FPGAs to be

View File

@ -295,6 +295,8 @@ int cxl_of_probe(struct platform_device *pdev)
int ret;
int slice = 0, slice_ok = 0;
dev_err_once(&pdev->dev, "DEPRECATION: cxl is deprecated and will be removed in a future kernel release\n");
pr_devel("in %s\n", __func__);
np = pdev->dev.of_node;

View File

@ -1726,6 +1726,8 @@ static int cxl_probe(struct pci_dev *dev, const struct pci_device_id *id)
int slice;
int rc;
dev_err_once(&dev->dev, "DEPRECATED: cxl is deprecated and will be removed in a future kernel release\n");
if (cxl_pci_is_vphb_device(dev)) {
dev_dbg(&dev->dev, "cxl_init_adapter: Ignoring cxl vphb device\n");
return -ENODEV;

View File

@ -4,10 +4,12 @@
#
config CXLFLASH
tristate "Support for IBM CAPI Flash"
tristate "Support for IBM CAPI Flash (DEPRECATED)"
depends on PCI && SCSI && (CXL || OCXL) && EEH
select IRQ_POLL
default m
help
The cxlflash driver is deprecated and will be removed in a future
kernel release.
Allows CAPI Accelerated IO to Flash
If unsure, say N.

View File

@ -3651,6 +3651,8 @@ static int cxlflash_probe(struct pci_dev *pdev,
int rc = 0;
int k;
dev_err_once(&pdev->dev, "DEPRECATION: cxlflash is deprecated and will be removed in a future kernel release\n");
dev_dbg(&pdev->dev, "%s: Found CXLFLASH with IRQ: %d\n",
__func__, pdev->irq);

View File

@ -20,7 +20,7 @@ static int test_gettimeofday(void)
gettimeofday(&tv_end, NULL);
}
timersub(&tv_start, &tv_end, &tv_diff);
timersub(&tv_end, &tv_start, &tv_diff);
printf("time = %.6f\n", tv_diff.tv_sec + (tv_diff.tv_usec) * 1e-6);

View File

@ -35,10 +35,18 @@
#define __NR_pkey_alloc 384
#define __NR_pkey_free 385
#ifndef NT_PPC_PKEY
#define NT_PPC_PKEY 0x110
#endif
#define PKEY_BITS_PER_PKEY 2
#define NR_PKEYS 32
#define PKEY_BITS_MASK ((1UL << PKEY_BITS_PER_PKEY) - 1)
#define AMR_BITS_PER_PKEY 2
#define PKEY_REG_BITS (sizeof(u64) * 8)
#define pkeyshift(pkey) (PKEY_REG_BITS - ((pkey + 1) * AMR_BITS_PER_PKEY))
inline unsigned long pkeyreg_get(void)
{
return mfspr(SPRN_AMR);

View File

@ -16,26 +16,7 @@
#include <unistd.h>
#include "ptrace.h"
#include "child.h"
#ifndef __NR_pkey_alloc
#define __NR_pkey_alloc 384
#endif
#ifndef __NR_pkey_free
#define __NR_pkey_free 385
#endif
#ifndef NT_PPC_PKEY
#define NT_PPC_PKEY 0x110
#endif
#ifndef PKEY_DISABLE_EXECUTE
#define PKEY_DISABLE_EXECUTE 0x4
#endif
#define AMR_BITS_PER_PKEY 2
#define PKEY_REG_BITS (sizeof(u64) * 8)
#define pkeyshift(pkey) (PKEY_REG_BITS - ((pkey + 1) * AMR_BITS_PER_PKEY))
#include "pkeys.h"
#define CORE_FILE_LIMIT (5 * 1024 * 1024) /* 5 MB should be enough */
@ -61,16 +42,6 @@ struct shared_info {
time_t core_time;
};
static int sys_pkey_alloc(unsigned long flags, unsigned long init_access_rights)
{
return syscall(__NR_pkey_alloc, flags, init_access_rights);
}
static int sys_pkey_free(int pkey)
{
return syscall(__NR_pkey_free, pkey);
}
static int increase_core_file_limit(void)
{
struct rlimit rlim;

View File

@ -7,26 +7,7 @@
*/
#include "ptrace.h"
#include "child.h"
#ifndef __NR_pkey_alloc
#define __NR_pkey_alloc 384
#endif
#ifndef __NR_pkey_free
#define __NR_pkey_free 385
#endif
#ifndef NT_PPC_PKEY
#define NT_PPC_PKEY 0x110
#endif
#ifndef PKEY_DISABLE_EXECUTE
#define PKEY_DISABLE_EXECUTE 0x4
#endif
#define AMR_BITS_PER_PKEY 2
#define PKEY_REG_BITS (sizeof(u64) * 8)
#define pkeyshift(pkey) (PKEY_REG_BITS - ((pkey + 1) * AMR_BITS_PER_PKEY))
#include "pkeys.h"
static const char user_read[] = "[User Read (Running)]";
static const char user_write[] = "[User Write (Running)]";
@ -61,11 +42,6 @@ struct shared_info {
unsigned long invalid_uamor;
};
static int sys_pkey_alloc(unsigned long flags, unsigned long init_access_rights)
{
return syscall(__NR_pkey_alloc, flags, init_access_rights);
}
static int child(struct shared_info *info)
{
unsigned long reg;

View File

@ -275,7 +275,7 @@ static struct test {
}
},
{
/* Parse a 32-bit value split accross two consecutives 64-bit
/* Parse a 32-bit value split across two consecutives 64-bit
* input values.
*/
"vphn: 16-bit value followed by 2 x 32-bit values",