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128 lines
4.1 KiB
Diff
128 lines
4.1 KiB
Diff
https://git.gnupg.org/cgi-bin/gitweb.cgi?p=libgcrypt.git;a=commit;h=9c93b4607adcf9b3efd53aba43e2d33bf5aef9df
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From 9c93b4607adcf9b3efd53aba43e2d33bf5aef9df Mon Sep 17 00:00:00 2001
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From: Jussi Kivilinna <jussi.kivilinna@iki.fi>
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Date: Sun, 4 Aug 2024 18:04:49 +0300
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Subject: [PATCH] mpi/ec-inline: reduce register pressure on 32-bit ARM
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* mpi/ec-inline.h [HAVE_COMPATIBLE_GCC_ARM_PLATFORM_AS] (ADD4_LIMB32)
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(ADD6_LIMB32, SUB4_LIMB32, SUB6_LIMB32): Reuse input registers
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as output (use just two unique operators).
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--
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This fixes building ec-nist.c with GCC-14 on 32-bit ARM.
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GnuPG-bug-id: 7226
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Signed-off-by: Jussi Kivilinna <jussi.kivilinna@iki.fi>
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--- a/mpi/ec-inline.h
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+++ b/mpi/ec-inline.h
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@@ -836,18 +836,18 @@ LIMB64_HILO(mpi_limb_t hi, mpi_limb_t lo)
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#ifdef HAVE_COMPATIBLE_GCC_ARM_PLATFORM_AS
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#define ADD4_LIMB32(A3, A2, A1, A0, B3, B2, B1, B0, C3, C2, C1, C0) \
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- __asm__ ("adds %3, %7, %11\n" \
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- "adcs %2, %6, %10\n" \
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- "adcs %1, %5, %9\n" \
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- "adc %0, %4, %8\n" \
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+ __asm__ ("adds %3, %3, %11\n" \
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+ "adcs %2, %2, %10\n" \
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+ "adcs %1, %1, %9\n" \
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+ "adc %0, %0, %8\n" \
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: "=r" (A3), \
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"=&r" (A2), \
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"=&r" (A1), \
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"=&r" (A0) \
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- : "r" ((mpi_limb_t)(B3)), \
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- "r" ((mpi_limb_t)(B2)), \
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- "r" ((mpi_limb_t)(B1)), \
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- "r" ((mpi_limb_t)(B0)), \
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+ : "0" ((mpi_limb_t)(B3)), \
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+ "1" ((mpi_limb_t)(B2)), \
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+ "2" ((mpi_limb_t)(B1)), \
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+ "3" ((mpi_limb_t)(B0)), \
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"Ir" ((mpi_limb_t)(C3)), \
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"Ir" ((mpi_limb_t)(C2)), \
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"Ir" ((mpi_limb_t)(C1)), \
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@@ -857,18 +857,18 @@ LIMB64_HILO(mpi_limb_t hi, mpi_limb_t lo)
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#define ADD6_LIMB32(A5, A4, A3, A2, A1, A0, B5, B4, B3, B2, B1, B0, \
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C5, C4, C3, C2, C1, C0) do { \
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mpi_limb_t __carry6_32; \
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- __asm__ ("adds %3, %7, %10\n" \
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- "adcs %2, %6, %9\n" \
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- "adcs %1, %5, %8\n" \
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- "adc %0, %4, %4\n" \
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+ __asm__ ("adds %3, %3, %10\n" \
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+ "adcs %2, %2, %9\n" \
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+ "adcs %1, %1, %8\n" \
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+ "adc %0, %0, %0\n" \
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: "=r" (__carry6_32), \
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"=&r" (A2), \
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"=&r" (A1), \
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"=&r" (A0) \
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- : "r" ((mpi_limb_t)(0)), \
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- "r" ((mpi_limb_t)(B2)), \
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- "r" ((mpi_limb_t)(B1)), \
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- "r" ((mpi_limb_t)(B0)), \
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+ : "0" ((mpi_limb_t)(0)), \
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+ "1" ((mpi_limb_t)(B2)), \
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+ "2" ((mpi_limb_t)(B1)), \
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+ "3" ((mpi_limb_t)(B0)), \
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"Ir" ((mpi_limb_t)(C2)), \
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"Ir" ((mpi_limb_t)(C1)), \
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"Ir" ((mpi_limb_t)(C0)) \
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@@ -878,18 +878,18 @@ LIMB64_HILO(mpi_limb_t hi, mpi_limb_t lo)
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} while (0)
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#define SUB4_LIMB32(A3, A2, A1, A0, B3, B2, B1, B0, C3, C2, C1, C0) \
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- __asm__ ("subs %3, %7, %11\n" \
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- "sbcs %2, %6, %10\n" \
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- "sbcs %1, %5, %9\n" \
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- "sbc %0, %4, %8\n" \
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+ __asm__ ("subs %3, %3, %11\n" \
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+ "sbcs %2, %2, %10\n" \
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+ "sbcs %1, %1, %9\n" \
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+ "sbc %0, %0, %8\n" \
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: "=r" (A3), \
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"=&r" (A2), \
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"=&r" (A1), \
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"=&r" (A0) \
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- : "r" ((mpi_limb_t)(B3)), \
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- "r" ((mpi_limb_t)(B2)), \
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- "r" ((mpi_limb_t)(B1)), \
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- "r" ((mpi_limb_t)(B0)), \
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+ : "0" ((mpi_limb_t)(B3)), \
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+ "1" ((mpi_limb_t)(B2)), \
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+ "2" ((mpi_limb_t)(B1)), \
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+ "3" ((mpi_limb_t)(B0)), \
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"Ir" ((mpi_limb_t)(C3)), \
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"Ir" ((mpi_limb_t)(C2)), \
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"Ir" ((mpi_limb_t)(C1)), \
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@@ -899,18 +899,17 @@ LIMB64_HILO(mpi_limb_t hi, mpi_limb_t lo)
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#define SUB6_LIMB32(A5, A4, A3, A2, A1, A0, B5, B4, B3, B2, B1, B0, \
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C5, C4, C3, C2, C1, C0) do { \
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mpi_limb_t __borrow6_32; \
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- __asm__ ("subs %3, %7, %10\n" \
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- "sbcs %2, %6, %9\n" \
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- "sbcs %1, %5, %8\n" \
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- "sbc %0, %4, %4\n" \
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+ __asm__ ("subs %3, %3, %9\n" \
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+ "sbcs %2, %2, %8\n" \
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+ "sbcs %1, %1, %7\n" \
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+ "sbc %0, %0, %0\n" \
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: "=r" (__borrow6_32), \
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"=&r" (A2), \
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"=&r" (A1), \
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"=&r" (A0) \
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- : "r" ((mpi_limb_t)(0)), \
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- "r" ((mpi_limb_t)(B2)), \
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- "r" ((mpi_limb_t)(B1)), \
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- "r" ((mpi_limb_t)(B0)), \
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+ : "1" ((mpi_limb_t)(B2)), \
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+ "2" ((mpi_limb_t)(B1)), \
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+ "3" ((mpi_limb_t)(B0)), \
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"Ir" ((mpi_limb_t)(C2)), \
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"Ir" ((mpi_limb_t)(C1)), \
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"Ir" ((mpi_limb_t)(C0)) \
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--
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2.30.2
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