59 lines
2.2 KiB
Diff
59 lines
2.2 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Kai Vehmanen <kai.vehmanen@linux.intel.com>
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Date: Thu, 3 Oct 2019 11:55:30 +0300
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Subject: [PATCH] drm/i915: Fix audio power up sequence for gen10+ display
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commit 1580d3cdddbba4a5ef78a04a5289e32844e6af24 upstream
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On platfroms with gen10+ display, driver must set the enable bit of
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AUDIO_PIN_BUF_CTL register before transactions with the HDA controller
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can proceed. Add setting this bit to the audio power up sequence.
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Failing to do this resulted in errors during display audio codec probe,
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and failures during resume from suspend.
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Note: We may also need to disable the bit afterwards, but there are
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still unresolved issues with that.
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Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111214
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Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
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Signed-off-by: Jani Nikula <jani.nikula@intel.com>
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Link: https://patchwork.freedesktop.org/patch/msgid/20191003085531.30990-1-kai.vehmanen@linux.intel.com
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---
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drivers/gpu/drm/i915/display/intel_audio.c | 5 +++++
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drivers/gpu/drm/i915/i915_reg.h | 2 ++
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2 files changed, 7 insertions(+)
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diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
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index 54638d99e021..e93776710abc 100644
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--- a/drivers/gpu/drm/i915/display/intel_audio.c
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+++ b/drivers/gpu/drm/i915/display/intel_audio.c
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@@ -862,6 +862,11 @@ static unsigned long i915_audio_component_get_power(struct device *kdev)
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/* Force CDCLK to 2*BCLK as long as we need audio powered. */
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if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
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glk_force_audio_cdclk(dev_priv, true);
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+
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+ if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
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+ I915_WRITE(AUD_PIN_BUF_CTL,
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+ (I915_READ(AUD_PIN_BUF_CTL) |
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+ AUD_PIN_BUF_ENABLE));
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}
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return ret;
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diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
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index eefd789b9a28..813ddea3f9f1 100644
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--- a/drivers/gpu/drm/i915/i915_reg.h
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+++ b/drivers/gpu/drm/i915/i915_reg.h
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@@ -9133,6 +9133,8 @@ enum {
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#define SKL_AUD_CODEC_WAKE_SIGNAL (1 << 15)
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#define AUD_FREQ_CNTRL _MMIO(0x65900)
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+#define AUD_PIN_BUF_CTL _MMIO(0x48414)
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+#define AUD_PIN_BUF_ENABLE REG_BIT(31)
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/*
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* HSW - ICL power wells
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--
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https://clearlinux.org
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